A. Field of the Invention
The present invention relates to systems and methods for identifying failure candidates for a failure analysis in a semiconductor apparatus, and more particularly, to systems and methods for identifying failure candidates with reduced execution time and improving efficiencies for identifying failure candidates in a failure analysis of a semiconductor apparatus.
B. Description of the Related Art
Failure analysis of a semiconductor integrated circuit (IC) may include physical analysis for detecting failure candidates, which may become failure causes of the IC among a large number of circuit nodes and circuit elements used in the IC. Failure analysis is performed based on measurement results of a tester that is very expensive.
Generally, it is very difficult to execute physical analysis many times for detecting failure candidates of a plurality of causes or at a plurality of portions in the same failure sample. Accordingly, in advance of performing a physical analysis, a restricting operation may be performed for minimizing the numbers of failure candidates. Usually, the failure candidates identifying operation is performed by comparing a failure dictionary produced by executing a failure simulation with actual measured results from a test equipment.
However, the conventional methods are labor and time intensive for performing the failure candidates restricting operation. Nevertheless, the conventional method frequently fails to analyze failure causes due to difficulties in restricting the numbers of failure candidates.
Recent fining technologies of semiconductor manufacture have rapidly developed for large scale integration and complication of circuits installed in one chip. Accordingly, the analysis for identifying failure candidates requires much more labor and time. Moreover, it becomes much more difficult to perform a failure candidates identifying operation due to multiple layers of wiring and complication of circuits in an IC.
To solve these difficulties of failure analysis, Japanese Patent Application Publication 2000-155156 (herein '156) has proposed a method for restricting the number of failure causes. The method proposed to restrict the number compares output expectation values of a failure simulation with actual measured results by a test equipment at each of several times.
However, the method of '156 has serious problems; for example, it occupies expensive test equipment for performing a failure analysis for a long time. In particular, if a plurality of failure causes exists in a subject IC, measurements of test patterns may be repeated for every time by the test equipment with back tracking selection of a following test pattern. This occupies the test equipment for a longer time in order to execute the failure analysis. Since the proposed method of 1156 restricts the number by comparing output expectation values of a failure simulation, it is hard to apply other failure causes, such as the Iddq failure, which occurs from an abnormal increase of source current while the device is stopped. Thus, the proposed method of '156 still has many problems.